The present invention relates generally to analog-to-digital converters (ADCs) and, more particularly, to an ADC that utilizes a weighted capacitor array.
An ADC utilizing a weighted capacitor array is disclosed in U.S. Pat. No. 4,200,863 to Hodges, et al. In that patent, the upper plates of the capacitor array are coupled to a common node and charged to -V.sub.in. The lower plates of each capacitor in the array are coupled to either a first or second reference voltage by an ordered set of code switches. The code switches are set to various binary states by a successive approximation control logic until the voltage at the common node is nulled. The state of the code switches when the voltage level at the common node is nulled indicates the digital representation of the voltage level V.sub.in.
As illustrated in FIG. 3 of that patent, six clock cycles may be utilized during the successive approximation technique to generate the digital representation of V.sub.in. Further, in the embodiment depicted in FIG. 17 of that patent, a resistor string digital to analog converter (DAC) is utilized to subdivide the second reference voltage into a set of reference voltage levels. Again, a successive approximation technique is utilized to determine the reference voltage level that approximates the V.sub.in signal.
The embodiment depicted in the above-described patent may be fabricated utilizing all MOS techniques. Thus, cost is reduced and yield is increased compared to conventional conversion techniques.
However, the successive approximation technique for dividing the second reference voltage and setting the digital codes of the code switches takes several clock cycles. Thus, this embodiment may not be fast enough for use in video, or other systems, requiring conversion at MHz frequencies.